The present invention relates to a picture processing apparatus for generating and displaying characters and graphical data. More particularly, the present invention relates to a picture processing apparatus having an integrated memory system, wherein a frame buffer for storing pixel data to be displayed is integrated in a main storage device, and to a picture processing method embraced by the picture processing apparatus.
An example of a picture processing apparatus having an the integrated memory system based on the prior art is disclosed in JPA4-84192. In this system, a priority control signal is used for notifying a memory control unit that a display circuit is about to make an access to the memory, taking precedence over other circuits. In reference to the priority control signal, the memory control unit executes control to raise the priority level of the access to the memory to be made by the display circuit. Thus, in this memory system, the control of memory accesses is executed so as to never interrupt the display of a picture on a display unit, such as a CRT, even if the number of contentions for an access to the memory increases due to integration of the memories.
In the apparatus described above, the priority control signal is provided as a means to enable a circuit, which has to always complete processing within a prescribed time, to make access to the memory, taking precedence over other circuits.
In the apparatus described above, however, no consideration is given to a configuration including a plurality of circuits, each of which has to always complete processing within a prescribed time. For example, consider a configuration including a display circuit and a video input circuit, each of which has to always complete processing within a prescribed time. In such a configuration, the display circuit has to read out data to be displayed from a memory so as to display data on a CRT in an uninterrupted manner. On the other hand, the video input circuit has to always write video input data, which is received continuously, into the memory so that no part of the video input data is missed. To be more specific, the display circuit has to read out all of the data of one screen to be displayed from the memory within a period of time it takes to display one screen. Similarly, the video input circuit has to always write all of the video input data of one screen within a period of time it takes to obtain the video input data of one screen. In order to apply the features described above to the picture processing apparatus including such a display circuit and such a video input circuit, it is thus necessary to provide a priority control signal to each of the display circuit and the video input circuit. When both the display circuit and the video input circuit assert the priority control signals to the memory control unit at the same time, the memory control unit eventually lets the circuit having a higher priority make access to the memory, raising a problem that the other circuit is not assured of the ability to make as many accesses to the memory as required to complete its processing within the prescribed time, even if the other circuit also activates the priority control signal.
It is thus an object of the present invention to provide a picture processing apparatus having an integrated memory system and including a plurality of circuits, each of which is required to always complete its processing within a prescribed time, wherein the circuits are each assured of the ability to make as many accesses to the memory as required to complete its processing within the prescribed time.
In order to achieve the object described above, there is provided a picture processing apparatus having:
a CPU for carrying out processing;
a memory for storing processing results produced by the CPU and data to be displayed;
a display control circuit for making accesses to the memory and for controlling an operation to display the data stored in the memory;
a processing circuit for completing processing within a prescribed time by making accesses to the memory to read out the data to be displayed; and
a bus control circuit for arbitrating a contention for an access to the memory between the display control circuit and the processing circuit, wherein:
the display control circuit and the processing circuit each have a means for outputting an internal-state signal representing an internal state thereof; and
the bus control circuit determines which of the display control and the processing circuit is to be given a higher priority to make an access to the memory on the basis of the internal-state signals output by the display control and the processing circuit.
In addition, the object described above can also be achieved by providing a picture processing apparatus having:
a CPU for carrying out processing;
a first memory for storing processing results produced by the CPU;
a second memory for storing processing results produced by the CPU and data to be displayed;
a display control circuit for making accesses to the second memory and for controlling an operation to display the data stored in the second memory;
a processing circuit for completing processing within a prescribed time by making accesses to the second memory to read out the data to be displayed; and
a bus control circuit for arbitrating a contention for an access to the second memory between the display control circuit and the processing circuit, wherein:
the display control circuit and the processing circuit each have a means for outputting an internal-state signal representing an internal state thereof; and
the bus control circuit determines which of the display control and the processing circuit is to be given a higher priority to make an access to the second memory on the basis of the internal-state signals output by the display control and the processing circuit.